Clock buffer circuit of semiconductor device

ABSTRACT

A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Korean patent applicationnumber 10-2006-0138768, filed Dec. 29, 2006, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device, and moreparticularly to a clock buffer circuit for buffering a clock signal.

In general, a semiconductor memory device, such as a dynamic randomaccess memory (DRAM), comprises a memory array including a plurality ofmemory cells for storing data.

Particularly, in a synchronous DRAM (SDRAM) among various DRAMs, a dataread/write operation is carried out synchronously with an external clocksignal. For this reason, in the SDRAM, there is a need for a clockbuffer circuit to generate an internal clock signal which is insynchronization with the external clock signal.

The clock buffer circuit for the SDRAM employs a differential amplifierto which a clock signal and an inverted clock signal having an oppositephase to that of the clock signal are inputted in tandem so that a clockduty ratio can be impervious to external noise.

Particularly, in semiconductor memory devices such as DDR/DDR2/DDR3SDRAMs, data is read/written synchronously with rising and falling edgesof a clock, so that it can be transmitted at a higher speed than in theexisting SDRAMs.

In order to accurately synchronize data with clock edges, a clockcontrol is required within a memory to generate an internal clock whoseduty ratio to the phase of an external clock is 50:50. Also, in order toensure an accurate output clock phase, there is a need for a dutycorrection circuit (DCC) to correct a duty error of an external clock orinternal clock. This DCC becomes more important in high-speed Quad DataRate (QDR: an operation mode where four data are equally outputtedduring one cycle) DRAMs.

On the other hand, a conventional clock buffer circuit 100, such as aquadri coupled receiver (QCR) buffer, as shown in FIGS. 1 and 2, must bedesigned to generate an internal clock signal ICLK having tR (time delayfrom external clock rising to internal clock rising)/tF (time delay fromexternal clock falling to internal clock falling) characteristics whichare always equal in any given conditions. However, in a practical chip,the tR/tF characteristics may not be equal due to various externalenvironmental factors, as shown in FIG. 3.

FIG. 4 illustrates variations in the tR/tF characteristics of the clockbuffer circuit of FIG. 2. From this drawing, it can be seen that thereis a tR/tF difference of 0.2 ns or more occurring with voltage drops(VDD variations) under the same input conditions. This means a dutydistortion due to buffering, which leads to an increase in externalparameters to be corrected by the DCC, resulting in a reduction inaccuracy of the DCC. As a result, this duty distortion deteriorates thehigh-speed operation of a memory device.

BRIEF SUMMARY OF THE INVENTION

In an aspect of the present invention, a clock buffer circuit of asemiconductor device comprises: a first clock buffer for receiving andbuffering a normal-phase clock signal; a second clock buffer forreceiving and buffering a reverse-phase clock signal; and an internalclock generator for generating an internal clock signal in response tooutput signals from the first and second clock buffers.

The internal clock generator may generate a rising edge of the internalclock signal at a rising edge of the buffered signal from the firstclock buffer, and a falling edge of the internal clock signal at arising edge of the buffered signal from the second clock buffer.

In another aspect of the present invention, a clock buffer circuit of asemiconductor device comprises an internal clock generator forgenerating a rising edge of an internal clock signal using a first clocksignal which is a buffered version of a normal-phase clock signal, and afalling edge of the internal clock signal using a second clock signalwhich is a buffered version of a reverse-phase clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a block diagram showing the configuration of a conventionalclock buffer circuit;

FIG. 2 is a detailed circuit diagram of the clock buffer circuit of FIG.1;

FIG. 3 is a timing diagram illustrating the operation of the clockbuffer circuit of FIG. 2;

FIG. 4 is a graph illustrating characteristic variations of the clockbuffer circuit of FIG. 2;

FIG. 5 is a block diagram showing the configuration of a clock buffercircuit according to an exemplary embodiment of the present invention;

FIG. 6 is a detailed circuit diagram of the clock buffer circuit of FIG.5;

FIG. 7 is a timing diagram illustrating the operation of the clockbuffer circuit of FIG. 5;

FIG. 8 is a detailed circuit diagram of an embodiment of an internalclock generator in FIG. 5;

FIG. 9 is a timing diagram illustrating the operation of the internalclock generator of FIG. 8;

FIG. 10 a detailed circuit diagram of an alternative embodiment of theinternal clock generator in FIG. 5;

FIG. 11 is a timing diagram illustrating the operation of the internalclock generator of FIG. 10; and

FIG. 12 is a graph illustrating characteristic variations of the clockbuffer circuit of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention will now be described indetail with reference to the accompanying drawings.

A clock buffer circuit of a semiconductor device according to thepresent invention is adapted to receive an external clock signal andgenerate an internal clock signal with no duty distortion, so thatexternal parameters to be corrected by a duty correction circuit (DCC)can be reduced, resulting in an increase in accuracy of the DCC.Therefore, it is possible to improve the high-speed operation andreliability of a memory device.

FIG. 5 is a block diagram showing the configuration of a clock buffercircuit according to an exemplary embodiment of the present invention,and FIG. 6 is a detailed circuit diagram of the clock buffer circuit ofFIG. 5.

As shown in FIG. 5, the clock buffer circuit according to thisembodiment comprises a first clock buffer 10 for receiving and bufferinga normal-phase clock signal CLK, a second clock buffer 20 for receivingand buffering a reverse-phase clock signal CLKB, and an internal clockgenerator 30 for generating an internal clock signal ICLK in response tooutput signals ICLKR and ICLKF from the first and second clock buffers10 and 20.

As shown in FIG. 6, the internal clock generator 30 generates a risingedge of the internal clock signal ICLK at a rising edge of the bufferedsignal ICLKR from the first clock buffer 10, and a falling edge of theinternal clock signal ICLK at a rising edge of the buffered signal ICLKFfrom the second clock buffer 20.

The internal clock generator 30 includes an edge trigger circuit.

The first clock buffer 10 includes a differential amplifier forreceiving the clock signal CLK as an input signal and the clock signalCLKB as a reference signal and amplifying and buffering a differencebetween the received signals.

The second clock buffer 20 includes a differential amplifier forreceiving the clock signal CLKB as an input signal and the clock signalCLK as a reference signal and amplifying and buffering a differencebetween the received signals.

FIG. 7 is a timing diagram illustrating the operation of the clockbuffer circuit of FIG. 5. The clock buffer circuit according to thepresent embodiment is adapted to generate the rising and falling edgesof the internal clock signal ICLK using the rising edges of the clocksignals CLK and CLKB. Therefore, it is possible to generate the internalclock signal with no duty distortion of the external clock signal.

In other words, the internal clock signal ICLK is generated byconverting the rising edge of the buffered version ICLKR of the clocksignal CLK into the rising edge of the internal clock signal and therising edge of the buffered version ICLKF of the clock signal CLKB intothe falling edge of the internal clock signal. At this time, a risingdelay time of the buffered version ICLKR of the clock signal CLK,namely, a time delay from external clock rising to internal clock rising(referred to hereinafter as “tR”), is equal to a tR of the bufferedversion ICLKF of the clock signal CLKB, so that the internal clocksignal with no duty distortion of the external clock signal can begenerated.

FIG. 8 is a detailed circuit diagram of an embodiment of the internalclock generator 30 in FIG. 5, and FIG. 9 is a timing diagramillustrating the operation of the internal clock generator 30 of FIG. 8.

As shown in FIG. 8, the edge trigger circuit includes a first inverter31 for buffering the output signal ICLKR from the first clock buffer 10,a first delay 32 for delaying an output signal from the first inverter31, a second delay 33 for delaying the output signal ICLKF from thesecond clock buffer 20, a driver 34 for performing a pull-up drivingoperation in response to the output signal from the first inverter 31and an output signal from the first delay 32 or a pull-down drivingoperation in response to the output signal ICLKF from the second clockbuffer 20 and an output signal from the second delay 33, a latch 35 forlatching an output signal from the driver 34, and a second inverter 36for buffering an output signal from the latch 35.

The driver 34 includes a first pull-up device P1 for performing thepull-up driving operation in response to the output signal from thefirst delay 32, a second pull-up device P2 connected in parallel to thefirst pull-up device P1 and acting to perform the pull-up drivingoperation in response to the output signal from the first inverter 31, afirst pull-down device N1 for performing the pull-down driving operationin response to the output signal ICLKF from the second clock buffer 20,and a second pull-down device N2 connected in parallel to the firstpull-down device N1 and acting to perform the pull-down drivingoperation in response to the output signal from the second delay 33.

Each of the first delay 32 and second delay 33 includes an odd number ofinverters.

FIG. 10 a detailed circuit diagram of an alternative embodiment of theinternal clock generator 30 in FIG. 5, and FIG. 11 is a timing diagramillustrating the operation of the internal clock generator 30 of FIG.10.

As shown in FIG. 10, the edge trigger circuit includes a first logiccircuit 41 for performing a logic operation with respect to the outputsignal ICLKR from the first clock buffer 10, a second logic circuit 42for performing a logic operation with respect to the output signal ICLKFfrom the second clock buffer 20, a first driver 43 for performing apull-up or pull-down driving operation in response to an output signalfrom the first logic circuit 41 and an inverted version of an outputsignal from the second logic circuit 42, a second driver 44 forperforming the pull-up or pull-down driving operation in response to aninverted version of the output signal from the first logic circuit 41and the output signal from the second logic circuit 42, a first outputunit 45 for outputting an output signal from the first driver 43, and asecond output unit 46 for outputting an output signal from the seconddriver 44.

The first logic circuit 41 includes a first delay 411 for delaying theoutput signal ICLKR from the first clock buffer 10, and a first logicdevice 412 for performing a NAND operation with respect to the outputsignal ICLKR from the first clock buffer 10 and an output signal fromthe first delay 411.

The second logic circuit 42 includes a second delay 421 for delaying theoutput signal ICLKF from the second clock buffer 20, and a second logicdevice 422 for performing the NAND operation with respect to the outputsignal ICLKF from the second clock buffer 20 and an output signal fromthe second delay 421.

The first driver 43 includes a first pull-up device P1 for performingthe pull-up driving operation in response to the output signal from thefirst logic circuit 41, a first pull-down device N1 for performing thepull-down driving operation in response to the output signal from thefirst logic circuit 41, and a second pull-down device N2 connected inparallel to the first pull-down device N1 and acting to perform thepull-down driving operation in response to the inverted version of theoutput signal from the second logic circuit 42.

The second driver 44 includes a second pull-up device P2 for performingthe pull-up driving operation in response to the output signal from thesecond logic circuit 42, a third pull-down device N3 for performing thepull-down driving operation in response to the output signal from thesecond logic circuit 42, and a fourth pull-down device N4 connected inparallel to the third pull-down device N3 and acting to perform thepull-down driving operation in response to the inverted version of theoutput signal from the first logic circuit 41.

The first output unit 45 includes a first latch 451 for latching theoutput signal from the first driver 43, and a first inverter 452 forbuffering an output signal from the first latch 451.

The second output unit 46 includes a second latch 461 for latching theoutput signal from the second driver 44, and a second inverter 462 forbuffering an output signal from the second latch 461.

The operation of the clock buffer circuit with the above-statedconfiguration according to the exemplary embodiment of the presentinvention will hereinafter be described with reference to FIGS. 5 to 12.

First, as shown in FIGS. 5 and 6, the first clock buffer 10 receives theclock signal CLK as an input signal and the clock signal CLKB as areference signal and amplifies and buffers a difference between thereceived signals. The second clock buffer 20 receives the clock signalCLKB as an input signal and the clock signal CLK as a reference signaland amplifies and buffers a difference between the received signals.

Then, the internal clock generator 30 generates a rising edge of theinternal clock signal ICLK at a rising edge of the buffered signal ICLKRfrom the first clock buffer 10, and a falling edge of the internal clocksignal ICLK at a rising edge of the buffered signal ICLKF from thesecond clock buffer 20. That is, the internal clock generator 30generates the internal clock signal ICLK by generating the rising andfalling edges of the internal clock signal ICLK using the rising edgesof the clock signals CLK and CLKB.

FIG. 8 shows the configuration of the exemplary embodiment of theinternal clock generator 30 in FIG. 5, and FIG. 9 illustrates theoperation of the internal clock generator 30 of FIG. 8.

As shown in FIG. 8, the internal clock generator 30 receives the outputsignal ICLKR from the first clock buffer 10 and the output signal ICLKFfrom the second clock buffer 20.

Then, the first inverter 31 buffers the output signal ICLKR from thefirst clock buffer 10, and the first delay 32 delays the output signalfrom the first inverter 31. The second delay 33 delays the output signalICLKF from the second clock buffer 20.

The driver 34 performs the pull-up driving operation in response to theoutput signal from the first inverter 31 and the output signal from thefirst delay 32 or the pull-down driving operation in response to theoutput signal ICLKF from the second clock buffer 20 and the outputsignal from the second delay 33.

At this time, as shown in FIGS. 8 and 9, the first pull-up device Pl ofthe driver 34 performs the pull-up driving operation in response to theoutput signal from the first delay 32. The second pull-up device P2,connected in parallel to the first pull-up device Pl, performs thepull-up driving operation in response to the output signal from thefirst inverter 31.

The first pull-down device N1 of the driver 34 performs the pull-downdriving operation in response to the output signal ICLKF from the secondclock buffer 20, and the second pull-down device N2, connected inparallel to the first pull-down device N1, performs the pull-downdriving operation in response to the output signal from the second delay33.

That is, as shown in FIG. 9, when the output signal ICLKR from the firstclock buffer 10 rises, nodes UP1 and UP2 become low in level in a delayperiod of the first delay 32, thereby causing the first and secondpull-up devices P1 and P2 to be turned on.

Also, when the output signal ICLKF from the second clock buffer 20rises, nodes DN1 and DN2 become high in level in a delay period of thesecond delay 33, thereby causing the first and second pull-down devicesN1 and N2 to be turned on.

Then, the latch 35 latches the output signal from the driver 34, and thesecond inverter 36 buffers the output signal from the latch 35.

In this manner, the internal clock signal ICLK is generated byconverting the rising edge of the buffered version ICLKR of the clocksignal CLK into the rising edge of the internal clock signal and therising edge of the buffered version ICLKF of the clock signal CLKB intothe falling edge of the internal clock signal.

FIG. 10 shows the configuration of the alternative embodiment of theinternal clock generator 30 in FIG. 5, and FIG. 11 illustrates theoperation of the internal clock generator 30 of FIG. 10.

As shown in FIG. 10, the internal clock generator 30 receives the outputsignal ICLKR from the first clock buffer 10 and the output signal ICLKFfrom the second clock buffer 20.

Then, the first logic circuit 41 performs the NAND operation withrespect to the output signal ICLKR from the first clock buffer 10 andthe output signal from the first delay 411, and the second logic circuit42 performs the NAND operation with respect to the output signal ICLKFfrom the second clock buffer 20 and the output signal from the seconddelay 421.

The first driver 43 performs the pull-up or pull-down driving operationin response to the output signal from the first logic circuit 41 and theinverted version of the output signal from the second logic circuit 42,and the second driver 44 performs the pull-up or pull-down drivingoperation in response to the inverted version of the output signal fromthe first logic circuit 41 and the output signal from the second logiccircuit 42.

That is, as shown in FIG. 11, at the moment that the output signal ICLKRfrom the first clock buffer 10 rises, a node A becomes low in level in adelay period of the first delay 411 and a node AB becomes high in levelin the same period, thereby causing the first pull-up device P1 and thethird and fourth pull-down devices N3 and N4 to be turned on.

Also, at the moment that the output signal ICLKF from the second clockbuffer 20 rises, a node B becomes low in level in a delay period of thesecond delay 421 and a node BB becomes high in level in the same period,thereby causing the first and second pull-down devices N1 and N2 and thesecond pull-up device P2 to be turned on.

In this manner, the internal clock signal ICLK is generated byconverting the rising edge of the buffered version ICLKR of the clocksignal CLK into the rising edge of the internal clock signal and therising edge of the buffered version ICLKF of the clock signal CLKB intothe falling edge of the internal clock signal.

FIG. 12 is a graph illustrating characteristic variations of the clockbuffer circuit of FIG. 5, more particularly variations in tR/tFcharacteristics with voltage drops (VDD variations) under the same inputconditions which are the same as those in FIG. 4. It can be seen fromFIG. 12 that the tR/tF difference is reduced by 75% (0.2 ns->0.05 ns) ofthat in FIG. 4.

As apparent from the above description, the clock buffer circuitaccording to the present invention can generate the rising and fallingedges of the internal clock signal ICLK using the rising edges of theclock signals CLK and CLKB. Therefore, it is possible to generate theinternal clock signal with no duty distortion of the external clocksignal. In other words, the internal clock signal ICLK is generated byconverting the rising edge of the buffered version ICLKR of the clocksignal CLK into the rising edge of the internal clock signal and therising edge of the buffered version ICLKF of the clock signal CLKB intothe falling edge of the internal clock signal.

At this time, the tR of the buffered version ICLKR of the clock signalCLK is equal to the tR of the buffered version ICLKF of the clock signalCLKB, so that the internal clock signal with no duty distortion of theexternal clock signal can be generated.

The generation of this internal clock signal leads to a reduction inexternal parameters to be corrected by a duty correction circuit (DCC),resulting in an increase in accuracy of the DCC. Therefore, it ispossible to improve the high-speed operation of a memory device.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. A clock buffer circuit of a semiconductor device comprising: a firstclock buffer configured to receive and buffer a normal-phase clocksignal; a second clock buffer configured to receive and buffer areverse-phase clock signal; and an internal clock generator configuredto generate an internal clock signal in response to output signals fromthe first and second clock buffers.
 2. The clock buffer circuitaccording to claim 1, wherein the internal clock generator generates arising edge of the internal clock signal at a rising edge of thebuffered signal from the first clock buffer, and a falling edge of theinternal clock signal at a rising edge of the buffered signal from thesecond clock buffer.
 3. The clock buffer circuit according to claim 2,wherein the internal clock generator comprises an edge trigger circuit.4. The clock buffer circuit according to claim 3, wherein the edgetrigger circuit comprises: a first inverter for buffering the outputsignal from the first clock buffer; a first delay for delaying an outputsignal from the first inverter; a second delay for delaying the outputsignal from the second clock buffer; a driver for performing a pull-updriving operation in response to the output signal from the firstinverter and an output signal from the first delay or a pull-downdriving operation in response to the output signal from the second clockbuffer and an output signal from the second delay; a latch for latchingan output signal from the driver; and a second inverter for buffering anoutput signal from the latch.
 5. The clock buffer circuit according toclaim 4, wherein the driver comprises: a first pull-up device forperforming the pull-up driving operation in response to the outputsignal from the first delay; a second pull-up device connected inparallel to the first pull-up device, the second pull-up deviceperforming the pull-up driving operation in response to the outputsignal from the first inverter; a first pull-down device for performingthe pull-down driving operation in response to the output signal fromthe second clock buffer; and a second pull-down device connected inparallel to the first pull-down device, the second pull-down deviceperforming the pull-down driving operation in response to the outputsignal from the second delay.
 6. The clock buffer circuit according toclaim 4, wherein each of the first delay and second delay comprises anodd number of inverters.
 7. The clock buffer circuit according to claim3, wherein the edge trigger circuit comprises: a first logic circuit forperforming a logic operation with respect to the output signal from thefirst clock buffer; a second logic circuit for performing a logicoperation with respect to the output signal from the second clockbuffer; a first driver for performing a pull-up or pull-down drivingoperation in response to an output signal from the first logic circuitand an inverted version of an output signal from the second logiccircuit; a second driver for performing the pull-up or pull-down drivingoperation in response to an inverted version of the output signal fromthe first logic circuit and the output signal from the second logiccircuit; a first output unit for outputting an output signal from thefirst driver; and a second output unit for outputting an output signalfrom the second driver.
 8. The clock buffer circuit according to claim7, wherein the first logic circuit comprises: a first delay for delayingthe output signal from the first clock buffer; and a first logic devicefor performing a NAND operation with respect to the output signal fromthe first clock buffer and an output signal from the first delay.
 9. Theclock buffer circuit according to claim 8, wherein the second logiccircuit comprises: a second delay for delaying the output signal fromthe second clock buffer; and a second logic device for performing theNAND operation with respect to the output signal from the second clockbuffer and an output signal from the second delay.
 10. The clock buffercircuit according to claim 7, wherein the first driver comprises: afirst pull-up device for performing the pull-up driving operation inresponse to the output signal from the first logic circuit; a firstpull-down device for performing the pull-down driving operation inresponse to the output signal from the first logic circuit; and a secondpull-down device connected in parallel to the first pull-down device,the second pull-down device performing the pull-down driving operationin response to the inverted version of the output signal from the secondlogic circuit.
 11. The clock buffer circuit according to claim 10,wherein the second driver comprises: a second pull-up device forperforming the pull-up driving operation in response to the outputsignal from the second logic circuit; a third pull-down device forperforming the pull-down driving operation in response to the outputsignal from the second logic circuit; and a fourth pull-down deviceconnected in parallel to the third pull-down device, the fourthpull-down device performing the pull-down driving operation in responseto the inverted version of the output signal from the first logiccircuit.
 12. The clock buffer circuit according to claim 7, wherein thefirst output unit comprises: a first latch for latching the outputsignal from the first driver; and a first inverter for buffering anoutput signal from the first latch.
 13. The clock buffer circuitaccording to claim 12, wherein the second output unit comprises: asecond latch for latching the output signal from the second driver; anda second inverter for buffering an output signal from the second latch.14. The clock buffer circuit according to claim 1, wherein the firstclock buffer comprises a differential amplifier for receiving thenormal-phase clock signal as an input signal and the reverse-phase clocksignal as a reference signal and amplifying and buffering a differencebetween the received signals.
 15. The clock buffer circuit according toclaim 1, wherein the second clock buffer comprises a differentialamplifier for receiving the reverse-phase clock signal as an inputsignal and the normal-phase clock signal as a reference signal andamplifying and buffering a difference between the received signals. 16.A clock buffer circuit of a semiconductor device comprising an internalclock generator for generating a rising edge of an internal clock signalusing a first clock signal which is a buffered version of a normal-phaseclock signal, and a falling edge of the internal clock signal using asecond clock signal which is a buffered version of a reverse-phase clocksignal.
 17. The clock buffer circuit according to claim 16, wherein theinternal clock generator generates the rising edge of the internal clocksignal at a rising edge of the first clock signal, and the falling edgeof the internal clock signal at a rising edge of the second clocksignal.
 18. The clock buffer circuit according to claim 16, wherein theinternal clock generator comprises an edge trigger circuit.